Layout correcting method and layout correcting system

摘要

A layout correcting method and a layout correcting system are provided. The layout correcting method includes the following steps. An integrated circuit design layout is provided. A plurality of performance parameters of the integrated circuit design layout are analyzed. A plurality of devices under test is selected according to the performance parameters. A computer simulating process is performed on the devices under test and a direct probing process is performed on the devices under test. The direct probing process is an on-chip test for comparing each device under test and an environment condition thereof by a Boolean algebra algorithm. A plurality of differences between the results of the computer simulating process and the direct probing process is analyzed. The integrated circuit design layout is corrected according to differences between the results of the computer simulating process and the direct probing process.

主权项

1. A layout correcting method, comprising:
providing an integrated circuit design layout; analyzing a plurality of performance parameters of the integrated circuit design layout; selecting a plurality of devices under test according to the performance parameters; performing a computer simulating process on the devices under test and performing a direct probing process on the devices under test, wherein the direct probing process is an on-chip test for comparing each device under test and an environment condition thereof by a Boolean algebra algorithm; analyzing a plurality of differences between the results of the computer simulating process and the direct probing process; and correcting the integrated circuit design layout according to differences between the results of the computer simulating process and the direct probing process.