发明名称 |
Method of manufacturing a non-volatile memory device having a vertical structure |
摘要 |
A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer. |
申请公布号 |
US8927366(B2) |
申请公布日期 |
2015.01.06 |
申请号 |
US201213610344 |
申请日期 |
2012.09.11 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Lee Sung-hae;Hwang Ki-hyun;Kim Jin-gyun |
分类号 |
H01L21/04;H01L27/115 |
主分类号 |
H01L21/04 |
代理机构 |
P. Chau & Associates, LLC |
代理人 |
P. Chau & Associates, LLC |
主权项 |
1. A method of manufacturing a non-volatile memory device, the method comprising:
alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer. |
地址 |
Suwon-Si, Gyeonggi-Do KR |