发明名称 |
Inverter circuit and display unit |
摘要 |
An inverter circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; an input terminal and an output terminal; and a capacitor. The capacitor is inserted between a gate of the second transistor and one of a source and a drain of the second transistor in which the one is located on an output terminal side. |
申请公布号 |
US8928647(B2) |
申请公布日期 |
2015.01.06 |
申请号 |
US201213406064 |
申请日期 |
2012.02.27 |
申请人 |
Sony Corporation |
发明人 |
Yamamoto Tetsuro;Uchino Katsuhide |
分类号 |
G06F3/038;G09G5/00;G09G3/00;G09G3/32 |
主分类号 |
G06F3/038 |
代理机构 |
Rader, Fishman & Grauer PLLC |
代理人 |
Rader, Fishman & Grauer PLLC |
主权项 |
1. An inverter circuit, comprising:
a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; an input terminal and an output terminal; and a capacitor, wherein the first transistor makes and breaks electrical connection between the output terminal and a first voltage line, in response to a potential difference between the input terminal and the first voltage line or to an equivalent thereto, the second transistor makes and breaks electrical connection between a second voltage line and the output terminal, in response to a potential difference between a source or a drain of the fourth transistor and the output terminal or to an equivalent thereto, the third transistor makes and breaks electrical connection between a gate of the second transistor and a third voltage line, in response to a potential difference between the input terminal and the third voltage line or to an equivalent thereto, the fourth transistor makes and breaks electrical connection between a first terminal equivalent to a source or a drain of the fifth transistor and the gate of the second transistor, in response to a first control signal inputted to a gate of the fourth transistor, the fifth transistor makes and breaks electrical connection between a fourth voltage line and the first terminal, in response to a second control signal inputted to a gate of the fifth transistor, and the capacitor is inserted between the gate of the second transistor and one of a source and a drain of the second transistor, the one being located on an output terminal side. |
地址 |
Tokyo JP |