发明名称 Input/output device
摘要 An input/output device includes a display circuit which changes its display state in accordance with a display data signal; a plurality of photodetector circuits which generate optical data in accordance with illuminance of light entering the photodetector circuits; wherein the photodetector circuits each include X (a natural number of 2 or more) photoelectric conversion elements; X charge accumulation control transistors in which one of a source and a drain is electrically connected to a second current terminal of one photoelectric conversion element of the X photoelectric conversion elements, and one charge accumulation control signal of X charge accumulation control signals from the photodetector circuit control section is input to the gate; and an amplifying transistor in which a gate is electrically connected to one of the source and the drain of each of the X charge accumulation control transistors.
申请公布号 US8928053(B2) 申请公布日期 2015.01.06
申请号 US201113217553 申请日期 2011.08.25
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kurokawa Yoshiyuki
分类号 H04N3/14;G06F3/041;G09G3/36 主分类号 H04N3/14
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A semiconductor device comprising: a pixel portion configured to display an image, the pixel portion comprising: a first photoelectric conversion element;a second photoelectric conversion element;a first transistor;a second transistor; anda third transistor; anda fourth transistor, wherein the first photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor, wherein the second photoelectric conversion element is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the third transistor, wherein the other of the source and the drain of the second transistor is electrically connected to the gate of the third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein the third transistor and the fourth transistor are electrically connected in series, and wherein each of the first transistor and the second transistor comprises an oxide semiconductor layer comprising a channel formation region.
地址 Atsugi-shi, Kanagawa-ken JP