发明名称 Method for parallel fine rasterization in a raster stage of a graphics pipeline
摘要 In a raster stage of a graphics processor, a method for parallel fine rasterization. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor. The graphics primitive is rasterized at a first level to generate a plurality of tiles of pixels. The titles are subsequently rasterized at a second level by allocating the tiles to an array of parallel second-level rasterization units to generate covered pixels. The covered pixels are then output for rendering operations in a subsequent stage of the graphics processor.
申请公布号 US8928676(B2) 申请公布日期 2015.01.06
申请号 US200611474027 申请日期 2006.06.23
申请人 Nvidia Corporation 发明人 Steiner Walter R.;Crow Franklin C.;Wittenbrink Craig M.;Allen Roger L.;Voorhies Douglas A.
分类号 G06F15/80;G06T15/00;G06T11/40 主分类号 G06F15/80
代理机构 代理人
主权项 1. In a raster stage of a graphics processor, a method for parallel fine rasterization comprising: receiving a graphics primitive for rasterization in a raster stage of a graphics processor; rasterizing the graphics primitive at a first level by using a first level rasterization unit to isolate a plurality of tiles sets within the graphics primitive, wherein each tile set comprises a plurality of pixels, wherein a first tile set of the plurality of tile sets corresponds to a second tile set based on a tile grouping formation determined for the graphics primitive, wherein the rasterizing at the first level is implemented on a per clock cycle basis; receiving the tile sets isolated by the coupled first level rasterization unit and rasterizing the tiles sets at a second level by allocating the tile sets to an array of parallel second-level rasterization units to generate covered pixels; and outputting the covered pixels for rendering operations in a subsequent stage of the graphics processor, wherein the array of parallel second-level rasterization units are capable of selective functional component activation, and wherein the selective functional component activation is operable to be responsive to an overall power consumption level of the graphics processor and wherein the selective functional component activation is operable to activate or deactivate a functional second level rasterization unit in relation to a target performance level of the rendering operations.
地址 Santa Clara CA US