High-linearity phase frequency detector

摘要

A phase frequency detector realizes a highly linear conversion from noise-shaped ΣΔ modulation into charge quantities without degradation of phase-locked loop (PLL) phase noise. The phase frequency detector may feature a construction of an Up signal output and a Down signal output, in which the Up signal rises when a divided VCO input rises, an Up signal falls when the divided VCO input falls, a Down signal rises when the divided VCO input rises, and a Down signal falls when a reference input rises. A mode selection input may be utilized for a fast lock-up PLL.

主权项

1. A phase frequency detector circuit, applied to a fractional-N synthesizer phase-locked loop (PLL) circuit comprising:
a charge-pump, a voltage-controlled oscillator (VCO) for providing a VCO output signal, an N-divider having an input for receiving the VCO output signal and for providing an N-divided output signal, a modulator for modulating the N-divided output signal, a reference frequency supply, and a loop filter, the phase frequency detector circuit comprising:
a first input for receiving a signal oscillating at a reference frequency,a second input for receiving the N-divided output signal,an Up signal output, anda Down signal output, wherein the Up signal output rises when the second input rises and falls when the second input falls, the Down signal output rises when the second input rises and falls when the first input rises, and the Down signal output does not rise and does not fall when the first input falls.