Transceiver, voltage control oscillator thereof and control method thereof

摘要

A transceiver includes a phase lock loop (PLL) and a clock data recovery circuit (CDR). The phase lock loop generates a first level control signal. The clock data recovery circuit, coupled to the phase lock loop, locks an incoming data signal to generate a data recovery clock according to a second level control signal. Wherein the clock data recovery circuit receives the first level control signal to further control a frequency range of the data recovery clock.

主权项

1. A transceiver, comprising:
a phase lock loop, comprising a first voltage controlled oscillator gain (KVCO), wherein the phase lock loop generates a first level control signal at a locked state according to a reference voltage; and a clock data recovery circuit, comprising a second KVCO, wherein the clock data recovery circuit is coupled to the phase lock loop, generates a second level control signal according to the second KVCO and a control voltage which is equal to the reference voltage, and locks an incoming data signal according to the first level control signal and the second level control signal to generate a data recovery clock; a comparator, wherein the comparator is coupled to the phase lock loop and the clock data recovery circuit; wherein a frequency range of the data recovery clock is determined by the first level control signal and the second level control signal, and wherein the phase lock loop comprises a first voltage control oscillator; the clock data recovery circuit comprises a second voltage control oscillator; the first voltage control oscillator generates a phase lock frequency signal according to the first level control signal; the second voltage control oscillator generates the data recover clock; and the comparator compares the frequency of the phase lock frequency signal with the frequency of the data recovery clock to generate a comparison result and the second voltage control oscillator adjusts the frequency of the phase lock frequency signal to be substantially equal to the frequency of the data recovery clock according to the comparison result and then the transceiver enables the clock data recovery circuit.