At-speed test of memory arrays using scan

摘要

A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC.

主权项

1. An integrated circuit (IC) comprising:
a memory array; a plurality of input circuits coupled to provide input signals into the memory array,
wherein each of the plurality of input circuits includes:an input flip-flop having a data output coupled to a corresponding input of the memory array;selection circuitry configured to select a data path to a data input of the input flip-flop; anda data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers and a plurality of flip-flops arranged in a serial configuration, wherein each of the plurality of multiplexers includes a first input coupled to an output of a corresponding unique preceding one of the plurality of flip-flops, wherein a second input of each of the plurality of multiplexers is coupled to an output of a last one of the plurality of flip-flops, wherein the selection circuitry is configured to select one of a true output or a complementary output from the input flip-flop based on an output signal provided by the last one of the plurality of flip-flops; and wherein, when operating in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC.