Three-dimensional memory device and operating method of a storage device including the same

摘要

A storage device is provided. The storage device includes a memory controller and at least one nonvolatile memory device including memory blocks having a pipe-shaped bit cost scalable (PBiCS) structure. Each of the memory blocks penetrates word lines stacked on a substrate in the form of plates and includes a first pillar, a second pillar, and a back-gate. The second pillar includes a semiconductor layer, an insulating layer, and a charge storage layer. The back-gate includes a pillar connection portion to connect the first and second pillars to each other and is disposed between the substrate and the word lines. The memory controller includes an adjacent cell management unit configured to control the at least one nonvolatile memory device such that a program operation, an erase operation or a read operation is performed on memory cells adjacent to the back-gate, unlike the other memory cells.

主权项

1. A three-dimensional (3D) memory device comprising:
memory blocks each including a plurality of strings, wherein each of the plurality of strings includes at least one string select transistor, first memory cells, a back-gate transistor, second memory cells, and at least one ground select transistor coupled in series between a bit line and a common source line, wherein each of the first and second memory cells includes a pillar-shaped semiconductor layer stacked in a direction perpendicular to a substrate, an insulating layer surrounding the semiconductor layer, a charge storage layer surrounding the insulating layer, and an insulating layer surrounding the charge storage layer; an address decoder configured to select one of the memory blocks in response to an address by driving a string select line connected to the string select transistor, word lines connected to the first and second memory cells, a back-gate line connected to the back-gate transistor, and a ground select line connected to the ground select transistor; a voltage generation circuit configured to generate voltages applied to the bit line, the common source line, the string select line, the word lines, the back-gate line, and the ground select line; an input/output circuit configured to provide data into the selected memory block or to read data from the selected memory block; and a control logic configured to control the address decoder, the voltage generation circuit, and the input/output circuit such that an adjacent cell operation on at least one memory cell adjacent to the back-gate transistor among the first and second memory cells of the selected memory block is made different from a normal cell operation on the other memory cells.