| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a PLL circuit that achieves both high jitter resistance to network jitter and a high clock synchronization convergence speed.SOLUTION: A time stamp provided at a transmission terminal side is extracted from a packet. A difference between the time stamp and a clock signal output by VOC is generated. On the basis of the difference, output characteristics of a PLL circuit is changed.</p> |
