CONFIGURABLE DECODER WITH APPLICATIONS IN FPGAS

摘要

The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address. The invention may include a second reconfigurable memory device that outputs the z-bit source word, based upon an x-bit source address input to the second memory device, where x

主权项

1. A bit-slice mapping unit, comprising: a circuit where the circuit has as input an z-bit source word having a binary value at each bit position, and an input selector address word, and said circuit forms an(nα)-bitword,nαbeing an integer and α is an integer ≧2, where n>z, where each(nα)-bitposition is hardwire connectable to an associated fixed subset of z-bit positions, where said binary value of each bit position of said(nα)-bitword is based upon said binary value of a selected one of the z-bit positions in said(nα)-bitpositions associated fixed subset, where said value of said selector address word selects said z-bit positions.