HYBRID MULTI-LEVEL MEMORY ARCHITECTURE

摘要

Hybrid multi-level memory architecture technologies are described. A System on Chip (SOC) includes multiple functional units and a multi-level memory controller (MLMC) coupled to the functional units. The MLMC is coupled to a hybrid multi-level memory architecture including a first-level dynamic random access memory (DRAM) (near memory) that is located on-package of the SOC and a second-level DRAM (far memory) that is located off-package of the SOC. The MLMC presents the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and provides the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM. The first-level DRAM does not store a copy of contents of the second-level DRAM.

主权项

1. A system on chip (SoC) comprising:
a plurality of functional units; and a multi-level memory controller (MLMC) for a hybrid multi-level memory architecture comprising a first-level dynamic random access memory (DRAM) that is located on-package of the SOC and a second-level DRAM that is located off-package of the SOC, wherein the MLMC is coupled to the plurality of functional units, wherein the MLMC is to present the first-level DRAM and the second-level DRAM as a contiguous addressable memory space and to provide the first-level DRAM to software as additional memory capacity to a memory capacity of the second-level DRAM, and wherein the first-level DRAM does not store a copy of contents of the second-level DRAM.