NOVEL NAND ARRAY ARCHITECTURE FOR MULTIPLE SIMUTANEOUS PROGRAM AND READ

摘要

This invention discloses a HiNAND array scheme with multiple-level of bit lines (BLs) including metal3 global bit lines (GBLs), divided metal2 Segment bit lines (SBLs), and divided metal1 block bit lines (BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines or power lines connected to bottoms of corresponding String capacitances of GBLs, SBLs, and BBLs are associated with metal0 line laid out perpendicular to those BLs. Under the HiNAND array scheme, conventional one-WL Read and Program-Verify operations are replaced by multiple-WL and All-BL Read and Program-Verify operations executed with charge capacitance of SBLs being reduced to 1/10- 1/20 of capacitance of GBLs to achieve DRAM-like faster operation, less operation stress, and lower power consumption. A preferred set of program biased voltages on the selected WL and remaining non-selected WLs associated with a Multiplier and a DRAM-like charge-sharing Latch Sensing Amplifier is proposed.

主权项

1. A high-density NAND (HiNAND) circuit with multi-level BL-hierarchical architecture for lowering disturbance, power-consumption, and latency in Program, Program-Verify, Erase-Verify, and Read operations, the HiNAND circuit comprising:
a matrix of NAND memory cells divided to J Groups in column-direction having N global bit lines (GBLs), each Group being divided to L Segments in the column-direction, each Segment being further divided to K Blocks in the column-direction, each Block comprising N Strings in the column-direction or M Pages in row-direction, each String comprising M NAND memory cells connected in series sandwiched by a first String-select transistor and a second String-select transistor, each NAND memory cell in a Page being associated with a word line (WL), J, L, K, M, and N being integer numbers, wherein J is at least equal to or greater than 8; a BL-hierarchical structure comprising N metal3 lines corresponding to N metal2 lines and further to N metal1 lines all being parallel to each other along the column-direction, each metal3 line being used as one the N GBLs across all J Groups of NAND memory cells, each metal2 line being used as one of N sub-BL lines (SBLs) associated with each column of NAND memory cells across all L Segments in each Group, each metal1 line being used as one of N sub-sub-BL lines (BBLs) across all K Blocks in each Segment; a plurality of metal0 lines laid out along the row-direction, the plurality of metal0 lines including at least one common source line connected respectively via the first String-select transistor to each of the N Strings of NAND memory cells in one or more Blocks of one or more Segments of each Group, a first power/Vss line for all J Groups, a second power/Vss line for all L Segments in a Group, and a third power/Vss line for all K Blocks in a pair of Segments in one Group; N first GBL-select transistors commonly controlled by a first gate signal to respectively couple the N GBLs with the first power/Vss line; N second GBL-select transistors commonly controlled by a second gate signal to respectively couple the N GBLs with the corresponding N SBLs; N first SBL-select transistors commonly controlled by a third gate signal to respectively couple the N SBLs with the second power/Vss line; N second SBL-select transistors commonly controlled by a fourth gate signal to respectively couple the N SBLs with the corresponding N BBLs; N BBL-select transistors commonly controlled by a fifth gate signal to respectively couple the N BBLs with the third power/Vss line; and a Page Buffer circuit respectively coupled to the N GBLs and configured to store and supply multiple logic page data in the form of sequential pipe-line; wherein the BL-hierarchical structure in accordance with a preferred set of bias voltage conditions associated with at least the first gate signal, the second gate signal, the third gate signal, the fourth gate signal, and the fifth gate signal is configured to allow temporary storages of program voltage and program-inhibit voltage in the multiple BBLs in one or more Segments of one or more Groups for performing multiple-WL and All-BL Program, Program-Verify, and Read operations simultaneously with less power, latency, and disturbance.