SRAM RESTORE TRACKING CIRCUIT AND METHOD

摘要

novel and useful SRAM restore tracking circuit adapted to improve the tracking of SRAM cell behavior for different PVT corners. The SRAM array access path is mainly influenced by two stages: (1) the wordline (WL) delay and (2) the SRAM cell delay. These two stages are usually the most sensitive for process variation in the memory access path. The restore tracking circuit incorporates two novel topologies for enhanced tracking to SRAM cell behavior. The first topology is a circuit that functions to mimic the wordline load and delay characteristics. The WL stage is very sensitive to process variation due to the large load it must drive and the usually relatively poor slope (i.e. depending on the number of cells the WL). The second topology is a circuit that mimics the SRAM cell load and delay characteristics. The SRAM cell is very sensitive to process variation due to its very small device features and the high number of cells in the memory array.

主权项

1. A method of static random access memory (SRAM) restore tracking in a SRAM array, said method comprising:
providing first circuitry operative to emulate wordline (WL) load and delay behavior; providing second circuitry, including a passgate transistor, operative to emulate SRAM cell load and delay behavior; and dynamically adjusting a bias voltage applied to the gate of said passgate transistor so as to compensate for threshold voltage (VT) mismatch among cells in said SRAM array.