发明名称 METHODS OF FABRICATING AN F-RAM
摘要 Non-volatile memory cells including complimentary metal-oxide-semiconductor transistors and embedded ferroelectric capacitor and methods of forming the same are described. In one embodiment, the method includes forming on a surface of a substrate a gate level including a gate stack of a MOS transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor. A local interconnect (LI) layer is deposited over the top surface of the first dielectric layer and the first contact, a ferro stack including a bottom electrode, a top electrode and ferroelectric layer there between deposited over the LI layer, and the ferro stack and the LI layer patterned to form a ferroelectric capacitor and a LI through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor.
申请公布号 US2015004718(A1) 申请公布日期 2015.01.01
申请号 US201314109045 申请日期 2013.12.17
申请人 Cypress Semiconductor Corporation 发明人 SUN Shan;RAMKUMAR Krishnaswamy;DAVENPORT Thomas;PATEL Kedar
分类号 H01L27/105;H01L49/02 主分类号 H01L27/105
代理机构 代理人
主权项 1. A method comprising: forming a gate level on a surface of a substrate, the gate level including a gate stack of a metal-oxide-semiconductor (MOS) transistor, a first dielectric layer overlying the MOS transistor and a first contact extending through the first dielectric layer from a top surface thereof to a diffusion region of the MOS transistor in the substrate; depositing a local interconnect (LI) layer over the top surface of the first dielectric layer and the first contact; depositing over the LI layer a ferroelectric layer and a top electrode; patterning the ferroelectric layer and top electrode to form a ferro stack; patterning the LI layer to concurrently form a ferroelectric capacitor comprising the ferro stack and a bottom electrode comprising a portion of the LI layer through which the bottom electrode is electrically coupled to the diffusion region of the MOS transistor, and a LI comprising an exposed portion of the LI layer not covered by the ferro stack; and concurrently encapsulating the ferroelectric capacitor and the LI with an encapsulation layer, wherein encapsulating the LI comprises depositing the encapsulation layer directly on a top surface and sidewalls of LI.
地址 San Jose CA US