| 发明名称 |
CHARGE ORDERED VERTICAL TRANSISTORS |
| 摘要 |
A vertical charge ordered transistor is disclosed. A thin charge ordered layer is employed as a tunnel barrier between two electrodes. A gate-induced accumulation of charge destabilizes the charge ordered state around the circumference of the device, opening up a parallel ohmic conduction channel, which leads to an exponential increase in source-drain current. VCOT devices have the potential to exhibit very large on/off ratios, low off-state currents, and sub-threshold slopes below 60 mV/dec. |
| 申请公布号 |
US2015001537(A1) |
申请公布日期 |
2015.01.01 |
| 申请号 |
US201314373267 |
申请日期 |
2013.02.15 |
| 申请人 |
RONDINELLI James;TAHERI Mitra;RAPPE Andrew Marshall;DEVLIN Robert Charles;The Trusteees of the University of Pennsylvania ;Drexel University |
发明人 |
May Steven;Spanier Jonathan;Rondinelli James;Taheri Mitra;Devlin Robert Charles;Rappe Andrew Marshall |
| 分类号 |
H01L29/24;H01L29/66;H01L29/78 |
主分类号 |
H01L29/24 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A vertical charge ordered transistor comprising:
a charge ordered layer; a source layer located adjacent the charge ordered layer; a drain layer located adjacent the charge ordered layer; a gate located adjacent to at least one of the layers; and a source electrode located on the source layer and a drain electrode located on the drain layer. |
| 地址 |
Philadelphia PA US |
