ARTIFICIAL NEURON COMPRISING A RESISTIVE MEMORY

摘要

A circuit for implementing an artificial neuron comprises: an integrator for an input signal to produce a voltage signal; a signal generator linked to the integrator output producing two output signals when the voltage is at or above a predetermined voltage, a first signal for an output pulse of the neuron and a second signal for a control pulse; a resistive memory comprising two terminals switching from a high to low resistance state in a time following a statistical distribution specific to the memory, a first terminal linked to the output of the integrator; a transistor linked to a branch at zero potential to a second terminal of the resistive memory, controlled by the second output signal such that in the presence of a pulse of voltage the resistive memory switches from its high resistance state to its low resistance state with a view to lowering the voltage.

主权项

1. A circuit for implementing an artificial neuron, said circuit comprising:
an integrator configured to integrate an input signal in such a way as to produce at the output a signal of voltage Vmem; a signal generator linked to the output of the integrator and configured to produce two output signals when the voltage Vmem is above or equal to a predetermined voltage Vth, a first signal corresponding to an output pulse of the neuron and a second signal corresponding to a control pulse Vout; a resistive memory comprising two terminals and able to switch from a high resistance state to a low resistance state in a time Tset following a statistical distribution specific to said memory, a first terminal being linked to the output of the integrator; and a transistor linked to a branch at zero potential as well as to a second terminal of the resistive memory, said transistor being furthermore configured to be controlled by the second output signal of the signal generator in such a way that in the presence of a pulse of voltage Vout the resistive memory switches from its high resistance state to its low resistance state with a view to lowering the voltage Vmem.