| 发明名称 |
CONDUCTIVE LINE PATTERNING |
| 摘要 |
A method includes placing two conductive lines in a layout. Two cut lines are placed over at least a part of the two conductive lines in the layout. The cut lines designate cut sections of the two conductive lines and the cut lines are spaced from each other within a fabrication process limit. The two cut lines are connected in the layout. The two conductive lines are patterned over a substrate in a physical integrated circuit using the two connected parallel cut lines. The two conductive lines are electrically conductive. |
| 申请公布号 |
US2015001734(A1) |
申请公布日期 |
2015.01.01 |
| 申请号 |
US201313930859 |
申请日期 |
2013.06.28 |
| 申请人 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
发明人 |
Liu Ru-Gun;Hsieh Tung-Heng;Tsai Tsung-Chieh;Wu Juing-Yi;Lee Liang-Yao;Ting Jyh-Kang |
| 分类号 |
H01L21/768;H01L23/528;G06F17/50;H01L23/522 |
主分类号 |
H01L21/768 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method, comprising:
placing two modeled conductive lines in a layout; placing two cut lines over at least a part of the two modeled conductive lines in the layout, wherein the cut lines designate cut sections of the two modeled conductive lines and the cut lines are spaced from each other within a fabrication process limit; connecting the two cut lines in the layout; and patterning two physical conductive lines disposed over a substrate in a physical integrated circuit using the two connected cut lines. |
| 地址 |
Hsin-Chu TW |
