STRESS-RESILIENT CHIP STRUCTURE AND DICING PROCESS

摘要

A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

主权项

1. A semiconductor structure comprising a semiconductor chip, said semiconductor chip including a semiconductor substrate and at least one dielectric material layer that embeds metal interconnect structures, wherein said at least one dielectric material layer includes:
pairs of parallel vertical surfaces, and corner surfaces that are not parallel to said pairs of parallel vertical surfaces and adjoin said pairs of parallel vertical surfaces.