发明名称 METHOD FOR PREPARING INSULATED GATE BIPOLAR TRANSISTOR OF TRENCH FS STRUCTURE
摘要 <p>A method for preparing an insulated gate bipolar transistor of a Trench FS structure comprises the following steps: forming an FS layer (20) on the back surface of a wafer (10); forming etching slots (12) on the front surface of the wafer (10), and forming a Pbody area precursor (14) between two adjacent etching slots (12); forming through deposition a dense gate oxide layer (30) on the etching slot (12); depositing a polycrystalline silicon gate (40) on the dense gate oxide layer (30); performing injection and spreading on the Pbody area precursor (14), to obtain a Pbody area (50), an area in which the Pbody area (50) directly contacts with the dense gate oxide layer (30) and that is exposed being referred to as a source area precursor (52); performing photoetching, injection, and spreading on the source area precursor (52), to obtain a source area (60); forming a medium block (70) on the front surface of the wafer (10); forming, on the front surface of the wafer (10), a source (16) and a gate (18) that are disposed at intervals; and forming a P+ anode layer (80) and a metal layer (90) on the back surface of the wafer (10). The method for preparing an insulated gate bipolar transistor of a Trench FS structure does not need an epitaxy technique, the productivity is high, and the cost is low.</p>
申请公布号 WO2014206177(A1) 申请公布日期 2014.12.31
申请号 WO2014CN78906 申请日期 2014.05.30
申请人 CSMC TECHNOLOGIES FAB1 CO., LTD. 发明人 WANG, GENYI;ZHANG, SHUO;RUI, QIANG;DENG, XIAOSHE
分类号 H01L21/331;H01L21/336;H01L21/8249 主分类号 H01L21/331
代理机构 代理人
主权项
地址