| 摘要 |
<p>The present invention relates to the field of integrated circuit test chips. Disclosed is a method for generating the layout of an addressable test chip, comprising the following steps: (1) selecting an IP; (2) according to a design rule, placing test structures into an array; and (3) automatically connecting the IP and the test structure array to a winding to generate the layout of a test chip. The present invention is automatically generated, according to the advantage of an addressable test and a test program, in accordance with design information, so that the test speed is fast and the test result is accurate. Software generated in the present invention can be applied to a parameter tester of intra-industry standards. The test accuracy of the present invention can reach the pA level. The automation generation of the present invention not only greatly shortens the development time of a test chip, reduces human resource costs, and avoids design errors caused by hand drawing, but also improves the extensibility and reusability of the addressable test chip, and provides a powerful guarantee for quickly coping with procedure changes and process node transitions.</p> |
