| 摘要 |
A microprocessor that uses an instruction word with only 4 opcode bits A (1), I (2), J (3) and M (4) in a RISC style architecture. The A, I and M opcode bits are also control signals to select outputs for multiplexers 63, 66, 67. The instruction word also includes immediate data idata (8,9,10) and up to three register addresses (destination register address DA (5), operand A register address AA (6) and operand B register address AB (7)). The arithmetic function performed by the arithmetic logic unit (ALU) 64 can be fixed or selected using the function select bus FS 74 based on the LSB of the immediate data. Instruction word sizes can be varied while making the programs binary compatible with each other by varying the sizes of the immediate data and register address bits only. |
