发明名称 |
Protection control apparatus |
摘要 |
A protection control apparatus includes a control-signal output circuit configured to generate a sampling signal in synchronization with a 1PPS signal and output, as a control signal, data numbers cyclically counted up every time the sampling signal is generated and the sampling signal and a data output unit configured to convert a system electrical quantity into digital data based on the control signal and output the digital data. The control-signal output circuit includes a number-of-clocks calculating circuit configured to calculate a second number of clocks and a third number of clocks and a synchronization control unit configured to calculate a difference between a first number of clocks and a second number of clocks, control a cycle of the sampling signal based on the difference and the third number of clocks, and synchronize generation timing of the sampling signal with the 1PPS signal. |
申请公布号 |
US8923361(B2) |
申请公布日期 |
2014.12.30 |
申请号 |
US201114350574 |
申请日期 |
2011.10.13 |
申请人 |
Mitsubishi Electric Corporation |
发明人 |
Oda Shigetoo |
分类号 |
H04B1/713;H04L7/00 |
主分类号 |
H04B1/713 |
代理机构 |
Buchanan Ingersoll & Rooney PC |
代理人 |
Buchanan Ingersoll & Rooney PC |
主权项 |
1. A protection control apparatus comprising a merging unit configured to merge system electric quantities detected in a power system, convert the system electric quantities into digital data, and output the digital data, the protection control apparatus protecting the power system, the protection control apparatus comprising:
the merging unit including:
a control-signal output circuit configured to generate a sampling signal in synchronization with a synchronization signal received from outside and output, as a control signal, numbers cyclically counted up every time the sampling signal is generated and the sampling signal; anda data output unit configured to convert the system electrical quantity into digital data based on the control signal output from the control-signal output circuit and output the digital data, wherein the control-signal output circuit includes:
a number-of-clocks calculating circuit configured to calculate, based on its own clocks of the number-of-clocks calculating circuit, a first number of clocks in time from a minimum to a maximum of the numbers, a second number of clocks in a cycle of the synchronization signal, and a third number of clocks in time from detection of the synchronization signal until the sampling signal is generated; anda synchronization control unit configured to calculate a difference between the first number of clocks and the second number of clocks, control a cycle of the sampling signal based on the difference and the third number of clocks, and synchronize the generation timing of the sampling signal with the synchronization signal. |
地址 |
Chiyoda-Ku, Tokyo JP |