Accommodating balance of bit line and source line resistances in magnetoresistive random access memory

摘要

A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances.

主权项

1. A magnetoresistive memory apparatus, comprising:
plural bit cells, each bit cell having at least one magnetoresistive element characterized by different resistances in different logic states of the bit cell, and each said bit cell occupying a bit cell position in a memory array having plural memory words, each memory word being addressable by a word line signal during a memory access operation involving one of reading from and writing to bit cells in the memory word; a read-write circuit for the bit cell position, the read/write circuit having one of an input and an output coupled to a bit line, and the bit cell being coupled between the bit line and a source line by at least one switching transistor when the bit cell is addressed during the memory access operation, wherein relative resistances of the bit line and the source line vary oppositely as a function of a location of the bit cell in the memory array; a drive control coupled to vary an input to the switching transistor as a function of the relative resistances of the bit line and the source line to offset a body effect caused by the location of the bit cell in the memory array.