Conditional ALU instruction condition satisfaction propagation between microinstructions in read-port limited register file microprocessor

摘要

An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.

主权项

1. A microprocessor having architectural condition flags and which performs an architectural instruction that instructs the microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only when the architectural condition flags satisfy a condition specified in the architectural instruction, the microprocessor comprising:
a register, that includes storage for the architectural condition flags and also contains storage for a non-architectural indicator; a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions; and an execution pipeline, that executes microinstructions received from the hardware instruction translator; wherein when executing the first microinstruction, the execution pipeline:
performs the operation on the source operands to generate the result;determines whether the architectural condition flags satisfy the condition; andupdates the non-architectural indicator to indicate whether the architectural condition flags satisfy the condition; wherein when executing the second microinstruction, the execution pipeline:
when the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, updates the destination register with the result; andwhen the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags do not satisfy the condition, updates the destination register with a current value of the destination register.