| 发明名称 | Semiconductor memory device | ||
| 摘要 | A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor. | ||
| 申请公布号 | US8923036(B2) | 申请公布日期 | 2014.12.30 |
| 申请号 | US201414171812 | 申请日期 | 2014.02.04 |
| 申请人 | Semiconductor Energy Laboratory Co., Ltd. | 发明人 | Saito Toshihiko |
| 分类号 | G11C11/24;G11C11/404;G11C11/56 | 主分类号 | G11C11/24 |
| 代理机构 | Fish & Richardson P.C. | 代理人 | Fish & Richardson P.C. |
| 主权项 | 1. A semiconductor memory device comprising: a bit line; a plurality of word lines; and a memory cell comprising a plurality of sub memory cells, the sub memory cells each comprising a transistor and a capacitor, wherein one of a source and a drain of the transistor is electrically connected to the bit line, wherein the other of the source and the drain of the transistor is electrically connected to the capacitor, wherein a gate of the transistor is electrically connected to one of the plurality of word lines, wherein a capacitance of a capacitor in a sub memory cell in the n-th row of the plurality of sub memory cells is 2n-1 times as large as a capacitance of a capacitor having a smallest capacitance of the capacitors, and wherein the n is a natural number. | ||
| 地址 | Atsugi-shi, Kanagawa-ken JP | ||