| 发明名称 | Merged floating point operation using a modebit | ||
| 摘要 | A first floating-point operation unit receives first and second variables and performs a first operation generating a first output. A first rounding unit receives and rounds the first output to generate a second output if a control bit is in a first state. A second floating-point operation unit receives a third variable and either the first output or the second output and performs a second operation on the third variable and either the first output or the second output, to generate a third output. The second floating-point operation unit receives and operates on the first output if the control bit is in the first state, or the second output if the control bit is in the second state. A second rounding unit receives and rounds the third output. | ||
| 申请公布号 | US8924454(B2) | 申请公布日期 | 2014.12.30 |
| 申请号 | US201213358399 | 申请日期 | 2012.01.25 |
| 申请人 | Arm Finance Overseas Limited | 发明人 | Lau David Yiu-Man |
| 分类号 | G06F7/483 | 主分类号 | G06F7/483 |
| 代理机构 | Patterson Thuente Pedersen, P.A. | 代理人 | Patterson Thuente Pedersen, P.A. |
| 主权项 | 1. A floating-point processing system comprising: a first storage unit configured to store a control bit having a first state and a second state; a first floating-point operation unit configured to receive a first floating-point variable and a second floating-point variable, and to perform a first floating-point operation on the first floating-point variable and the second floating-point variable so as to generate a first floating-point output having a first precision; a first rounding unit responsive to the control bit and configured to receive and round the first floating-point output if the control bit is in the first state so as to generate a second floating-point output having a second precision being less than the first precision; and a second floating-point operation unit configured to receive a third floating-point variable, and either the first floating-point output if the control bit is in the second state or the second floating-point output if the control bit is in the first state, the second floating-point operation unit further configured to perform a second floating-point operation on the third floating-point variable and either the first floating-point output or the second floating-point output so as to generate a third floating-point output having a third precision. | ||
| 地址 | Cambridge GB | ||