Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same

摘要

Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.

主权项

1. A method for fabricating an integrated circuit comprising:
forming a first fin and a second fin adjacent to each other extending from a semiconductor substrate; selectively epitaxially growing a silicon-containing material on the first and second fins to form a first epi-portion overlying a first upper section of the first fin and a second epi-portion overlying a second upper section of the second fin, wherein the first and second epi-portions are spaced apart from each other; forming a first silicide layer overlying the first epi-portion and a second silicide layer overlying the second epi-portion, wherein the first and second silicide layers are spaced apart from each other to define a lateral gap; depositing a dielectric material overlying the first and second silicide layers to form a dielectric spacer that spans the lateral gap; removing the dielectric material that overlies portions of the first and second silicide layers laterally above the dielectric spacer while leaving the dielectric spacer intact; and depositing a contact-forming material overlying the dielectric spacer and the portions of the first and second silicide layers.