Circuitry for padded communication protocols

摘要

Transmitter and receiver circuitry for 64b/66b encoding or other similar padded data signalling. The required transmitter clock circuitry is simplified by using one clock signal source as a basis for at least partly processing the data both before and after padding. Appropriate frequency multiplication and division factors are employed to make this possible. Similar techniques are used in receiver circuitry.

主权项

1. Apparatus for padding and transmitting initially unpadded blocks of data, the apparatus comprising:
means for deriving from a single reference clock signal first and second further clock signals having respective, different, first and second frequencies, wherein:
the first frequency being suitable for use of the first further clock signal in at least some processing of the unpadded blocks in a transmitter circuitry, andthe second frequency being suitable for use of the second further clock signal in at least some processing of the padded blocks in the transmitter circuitry, andbits of each of the padded blocks are assembled in parallel in the transmitter circuitry for transmission to a receiver, a deserializer configured to deserialize the unpadded blocks in the transmitter circuitry based on the first further clock signal, a register group configured to pad the deserialized unpadded blocks to obtain padded blocks, and a serializer configured to serialize the padded blocks in the transmitter circuitry based on the second further clock signal.