Methods and apparatus for clock tree phase alignment

摘要

Clock alignment circuitry may include phase comparator circuitry with a first input terminal that receives as first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree. The phase comparator circuitry may compare the first and second clock signals and generate different control signals based on the first and second clock signals. The integrated circuit may further include phase interpolator circuitry that generates an output clock signal based on at least one of the control signals received from the phase comparator circuitry. Edges of the generated output clock signal may align with edges of either the first clock signal or the second clock signal.

主权项

1. Clock alignment circuitry comprising:
phase comparator circuitry having a first input terminal that receives a first clock signal from a first clock tree and a second input terminal that receives a second clock signal from a second clock tree, wherein the phase comparator circuitry compares the first and second clock signals and outputs corresponding first and second control signals; and phase interpolator circuitry that receives a third clock signal and that generates an output clock signal that is aligned with one of the first and second clock signals based on at least one of the first and second control signals, wherein the first clock signal comprises a loopback version of the third clock signal being routed through the first clock tree.