Memory device for providing data in a graphics system and method and apparatus therof

摘要

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.

主权项

1. An apparatus comprising:
unified memory; and a memory controller operatively coupled to the unified memory via a plurality of memory channels, the memory controller operative to arbitrate access to at least a portion of the unified memory among a plurality of client data access requests from a plurality of clients to the plurality of memory channels and to bypass arbitration of the plurality of client data access requests to said at least a portion of the unified memory in response to a CPU data access request to said at least a portion of the unified memory, the plurality of memory channels being accessible by the CPU through the memory controller, wherein the memory controller controls each memory channel to access client data address space and CPU data address space of the unified memory simultaneously.