Display pipe request aggregation

摘要

A system and method for efficiently scheduling memory access requests. A semiconductor chip includes a memory controller for controlling accesses to a shared memory and a display controller for processing frame data. In response to detecting an idle state for the system and the supported one or more displays, the display controller aggregates memory requests for a given display pipeline of one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller. Arbitration may be performed while the given display pipeline sends the aggregated memory requests. In response to not receiving memory access requests from the functional blocks or the display controller, the memory controller may transition to a low-power mode.

主权项

1. An apparatus comprising:
a memory controller configured to control access to a shared memory; and a display controller comprising one or more display pipelines configured to read frame data stored in the shared memory for an image to be presented on a display, wherein in response to determining an aggregate condition is satisfied, the display controller is configured to aggregate a first number of memory requests for a given display pipeline of the one or more display pipelines prior to attempting to send any memory requests from the given display pipeline to the memory controller.