Using backside passive elements for multilevel 3D wafers alignment applications

摘要

Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.

主权项

1. A device comprising:
a first integrated circuit die including:
a first semiconductor layer;a first dielectric layer on the first semiconductor layer;a first inductor coil in the first dielectric layer; and a second integrated circuit die coupled to the first integrated circuit die, the second integrated circuit die including:
a second semiconductor layer;a second dielectric layer on the second semiconductor layer; anda second inductor coil in the second dielectric layer, the first inductor coil in direct physical and electrical contact with the second inductor coil.