SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which effectively prevents characteristic deterioration due to a pattern shift in gate formation while suppressing increase in cell area, and reduces resistance in a power voltage supply line.SOLUTION: In a semiconductor memory device, each memory cell comprises two inverters respectively composed of first conductivity type driving transistors Qn1 and Qn2 and second conductivity type load transistors Qp1 and Qp2, which are electrically connected in series between a first power voltage supply line VCC and a second power voltage supply line VSS, and where gates are connected in common and input and output are connected by cross. At least one of the first power voltage supply line VCC and the second power voltage supply line VSS is composed of groove wiring formed by filling inside of a through groove in an inter-layer insulating layer with conductive material.