| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory controller capable of correcting a delay circuit without causing degradation in system performance.SOLUTION: A memory controller includes: delay circuits 12 to 14 connected to a memory 22 and each capable of making variable a setting of an output delay value per terminal; a DLL (Delay Locked Loop) 16 including a delay element identical in delay characteristics to the delay circuits 12 to 14; a first register 18 holding an output value in a locked state of the DLL 16 at arbitrary timing as a register value; second registers 19 to 21 each holding a delay set value per terminal as a register value; and a delay calculation circuit 17 calculating a delay value on the basis of an output value from the DLL 16, the register value of the first register 18, and the register values of the second registers 19 to 21. The delay calculation circuit 17 overwrites the calculation result on the register values of the second registers 19 to 21. |
