| 发明名称 |
TRANSITION RATE CONTROLLED BUS DRIVER CIRCUIT WITH REDUCED LOAD SENSITIVITY |
| 摘要 |
A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low). |
| 申请公布号 |
US2014380065(A1) |
申请公布日期 |
2014.12.25 |
| 申请号 |
US201313923339 |
申请日期 |
2013.06.20 |
| 申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
Halbert Joel Martin;Agarwal Vinay |
| 分类号 |
G06F1/32 |
主分类号 |
G06F1/32 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A circuit, comprising:
a signal lead; a reference terminal; a first transistor having a first control terminal and having a first current path coupled to the reference terminal; a second transistor having a second control terminal coupled to the first control terminal and having a second current path coupled between the signal lead and the reference terminal; a third transistor arranged to provide a first current through the first current path when the signal lead is in a first logic state; and a fourth transistor arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state. |
| 地址 |
Dallas TX US |
