发明名称 半導体集積回路およびそのパターンレイアウト方法
摘要 PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of forming a TEG (a Test Elementary Group) pattern by preventing that monitoring result has an error without reducing monitored items and without making width of a scribing region larger by using a dummy pattern.SOLUTION: A semiconductor integrated circuit comprises: a plurality of function modules formed in a chip; and a functional dummy pattern 5 formed in a peripheral vacant region 3 of a predetermined function module 2 in the chip and having an aberration monitoring function. The functional dummy pattern 5 is formed so that a band-shaped metal portion B and a band-shaped insulating film portion L are periodically repeated respectively in a plan view.
申请公布号 JP5647328(B2) 申请公布日期 2014.12.24
申请号 JP20130254057 申请日期 2013.12.09
申请人 发明人
分类号 H01L21/822;H01L21/82;H01L27/04 主分类号 H01L21/822
代理机构 代理人
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