Analog-to-digital conversion in pixel arrays

摘要

An analog-to-digital converter (51) for generating an output digital value equivalent to the difference between a first analog signal level (Vres) and a second analog signal level (Vsig) comprises at least one input (81) for receiving the first analog signal level and the second analog signal level, an input (82) for receiving a ramp signal and an input (83) for receiving at least one clock signal. A set of N counters, where N≥2, are arranged to use N clock signals which are offset in phase from one another. A control stage (57) is arranged to enable the N counters based on a comparison of the ramp signal with the first analog signal level (Vres) and the second analog signal level (Vsig). An output stage (65, 66) is arranged to output the digital value which is a function of values accumulated by the N counters during a period when they are enabled.