发明名称 マルチコア・アーキテクチャのためのユーザレベル割り込み機構
摘要 A method includes accepting for a first processor core of a plurality of processor cores in a multi-core system, a user-level interrupt indicated by a user-level interrupt message when an interrupt domain of an application thread executing on the first processor core and a recipient identifier of the application thread executing on the first processor core match corresponding fields in the user-level interrupt message.
申请公布号 JP5646628(B2) 申请公布日期 2014.12.24
申请号 JP20120524751 申请日期 2010.08.05
申请人 发明人
分类号 G06F9/48 主分类号 G06F9/48
代理机构 代理人
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