| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that a conventional operation synthesis system cannot generate an RTL description for attaining loop processing of high efficiency. SOLUTION: The operation synthesis system includes: an inter-loop dependency analysis processing part 21 which generates inter-loop dependency information by extracting execution conditions of dependency loop processing having dependency with other loop processing; a scheduling binding processing part 22 which determines a control step of executing operations in the loop processing and determines computing elements to perform the operations in the loop processing and registers to store data; a control circuit generation processing part 23 which generates a control circuit including first control logic to control an execution state of the control step in the loop processing and second control logic to control an execution state of the loop processing based upon the execution conditions of the loop processing; and an RTL description generation processing part 24 which generates a data path using the computing elements and registers, and generates an RTL description including the data path and control circuit. COPYRIGHT: (C)2012,JPO&INPIT |
