| 摘要 |
<p>A method of executing an instruction stream in a pipelined execution unit of depth, p, comprises loading the instruction stream; detecting an iteration of an instruction in the loaded instruction stream; interleaving p steams of instances of the instruction in the pipeline; detecting an end of the iteration; and combining results obtained from the p streams after all programmed iterations have completed. A computational circuit comprises a register which can hold a value representing both an operand and result of an iterative operation; a multiplexer having a first input connected to receive the operand from the register, a second input connected to a source of an identify value for the iterative operation, and an output; and an operator circuit having an input connected to receive a value from the multiplexer output, and an output connected to return thee result to the register. A method of executing an instruction stream in a pipelined execution unit comprises providing to the execution unit the instruction stream as a sequence of instruction in natural order absent software scheduling; detecting an iteration of an instruction in the sequence of instruction; and introducing into a pipeline of the pipelined execution unit plural instances of the iterated instruction, each with different data. A method of executing an instruction stream in a pipelined execution unit comprises detecting an iteration of an instruction in the instruction stream; independently executing plural streams of the iterated instruction; and recombining the independently executed plural streams to provide a single result; wherein independently executing and recombining use not more than one destination register and not more than one temporary register. In a programmable data processor including instruction interlocks and including a pipelined computation unit having a pipeline of depth p, a circuit comprises a controller constructed and arranged to detect an iterative computation in an incoming instruction stream.</p> |
