Superior integrity of high-k metal gate stacks by capping STI regions

摘要

When forming high-k metal gate electrode structures in an early manufacturing stage, integrity of an encapsulation and, thus, integrity of sensitive gate materials may be improved by reducing the surface topography of the isolation regions. To this end, a dielectric cap layer of superior etch resistivity is provided in combination with the conventional silicon dioxide material.

主权项

1. A method, comprising:
forming a dual layer patterned hard mask layer comprised of a first mask layer formed on a surface of a semiconductor layer and a second mask layer formed on said first mask layer; forming a trench through said dual layer patterned hard mask layer and into said semiconductor layer; forming a trench isolation region in said semiconductor layer of a semiconductor device by using a first dielectric material, said trench isolation region laterally delineating an active region in said semiconductor layer; with said dual layer patterned hard mask in position, including said second mask layer, forming a cap layer on the trench isolation region comprised of said first dielectric material by overfilling said trench with a second dielectric material, said first and second dielectric materials having different material composition; removing said second hard mask layer while leaving said first hard mask layer positioned on said surface of said semiconductor layer; with said first hard mask layer in position, performing a recess etching process on said cap layer comprised of said second dielectric material so as to thereby define a recessed cap layer having an upper surface that is positioned at a level that is below an upper surface of said first hard mask layer; completely removing said first hard mask layer so as to thereby expose said surface of said semiconductor layer; and after completely removing said first hard mask layer, forming a gate electrode structure on said active region and said cap layer.