Data processing apparatus

摘要

In the configuration performing a data processing by a hardware processing circuit (accelerator), to provide a technology capable of improving a poorness of processing efficiency by multiple accesses to the data, the following solving means are provided. A network data processing accelerator of the present network data processing apparatus comprises processing units corresponding to each processing of an encryption/decryption, a message authentication, and a checksum, and in the data processing including a combination of each processing, accesses for the same data of the memory and the like through a bus I/F unit and the like is collected together into one time, and a pipeline processing is performed using the least common multiple of the data processing unit of each processing.

主权项

1. A data processing apparatus comprising:
a central processing unit (CPU); a memory unit; an encryption/decryption processor constructed to perform an encryption and/or decryption type of data processing; a message authentication (MA) processor constructed to perform a message authentication type of data processing; and a checksum processing (CS) unit constructed to perform a checksum type of data processing; a bus interface (I/F) unit constructed to enable communication between the central processing unit (CPU) and/or the memory unit on one end, and the encryption/decryption processor and/or the message authentication processor and/or the checksum processor on the other end; wherein the data processing apparatus is configured, in a predetermined data processing, to execute in parallel and/or sequentially at least two of the aforementioned types of data processing in their respective processors, and to subject the at least two of the aforementioned types of data processing to a pipeline processing in multiple divided periods; wherein the data processing apparatus is configured to consolidate a plurality of overlapping data accesses into one access, for use in the predetermined data processing; and wherein the data processing apparatus is configured to determine a unified data processor (M) as a least common multiple of processing capacity, as measured in bytes, of the at least two of the encryption/decryption processor, the authentication processor, and the checksum processor.