发明名称 |
Semiconductor memory having non-standard form factor |
摘要 |
A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio. |
申请公布号 |
US8918702(B2) |
申请公布日期 |
2014.12.23 |
申请号 |
US201313926226 |
申请日期 |
2013.06.25 |
申请人 |
Infineon Technologies AG |
发明人 |
Vogelsang Thomas |
分类号 |
H03M13/00;G06F11/10;H03M13/29;H03M13/19 |
主分类号 |
H03M13/00 |
代理机构 |
|
代理人 |
Economou John S. |
主权项 |
1. A semiconductor memory chip comprising:
logic circuitry employing a binary external page size to send/receive data bits to/from external devices, the binary external page size comprising a binary number of data bits; error correction logic configured encode one or more groups of data bits of a page of data received from the logic circuitry to form coded words that together form a non-binary internal page size comprising a non-binary number of data bits, including the data bits of the one or more groups of data bits and error correction bits; and a plurality of memory cell arrays configured to store the coded words, each having a non-binary number of wordlines based on the non-binary internal page size arranged to provide the memory cell block with an aspect ratio of other than 2:1. |
地址 |
Neubiberg DE |