Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory

摘要

A memory device, and a method of forming a memory device, is provided that includes a capacitor with a lower electrode of a metal semiconductor alloy. In one embodiment, the memory device includes a trench present in a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer. A capacitor is present in the trench, wherein the capacitor includes a lower electrode of a metal semiconductor alloy having an upper edge that is self-aligned to the upper surface of the base semiconductor layer, a high-k dielectric node layer, and an upper electrode of a metal. The memory device further includes a pass transistor in electrical communication with the capacitor.

主权项

1. A method of forming a trench structure comprising:
providing a semiconductor substrate including a semiconductor on insulating (SOI) layer on top of a buried dielectric layer, wherein the buried dielectric layer is on top of a base semiconductor layer; forming a trench to a first depth in the semiconductor substrate, wherein the first depth of the trench extends through the SOI layer and the buried dielectric layer terminating on the base semiconductor layer; forming a dielectric spacer on sidewalls of the trench, wherein the dielectric spacer extends to an upper surface of the base semiconductor layer; extending the trench to a second depth into the base semiconductor layer of the semiconductor substrate; forming a metal-containing layer comprising a metal nitride on the sidewalls of the trench and a base of the trench, wherein the metal-containing layer is in direct contact with the base semiconductor layer of the semiconductor substrate; converting the metal-containing layer that is in direct contact with the base semiconductor layer into a metal semiconductor alloy lower electrode, wherein an upper edge of the metal semiconductor alloy lower electrode is aligned to the upper surface of the base semiconductor layer, wherein the converting of the metal-containing layer into the metal semiconductor alloy lower electrode comprises a two stage annealing process, wherein a first stage of the two stage annealing process converts the metal nitride to element metal, and a second stage of the two stage annealing process converts the element metal to a metal silicide where the metal silicide is in direct contact with the sidewalls and base of the trench in the base semiconductor layer; forming a dielectric layer at least on the metal semiconductor alloy lower electrode; and forming an upper electrode on the dielectric layer.