Chip package and manufacturing method thereof

摘要

An embodiment provides a chip package including a substrate, a cavity extending downward from an upper surface of the substrate, a metal layer overlying the substrate and conformally covering a sidewall and a bottom portion of the cavity, a chip having an upper surface and located on the metal layer in the cavity, wherein the upper surface is not lower than an upper surface of the metal layer outside of the cavity, and the protective layer covering the chip.

主权项

1. A method of forming a chip package, comprising:
providing a temporary substrate; forming a first soft insulating layer overlying the temporary substrate; bonding at least one chip overlying the first soft insulating layer; hardening the first soft insulating layer to form a first insulating layer; forming a metal layer overlying the temporary substrate, wherein the metal layer conformally covers the first insulating layer and the chip; forming a dielectric layer overlying the metal layer; removing the temporary substrate; removing the first insulating layer; and forming a protective layer overlying the chip.