Mesochronous signaling system with clock-stopped low power mode

摘要

In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.

主权项

1. A memory controller comprising:
driver circuitry to output a first timing signal to a memory device, the first timing signal to time transmission of a data signal from the memory device to the memory controller; control circuitry to enable oscillation of the first timing signal at a first frequency if a control signal is in a first state and to disable oscillation of the first timing signal if the control signal is in a second state; and clock generation circuitry to generate the first timing signal and to generate a controller-core clock signal that oscillates at a frequency other than the first frequency, and wherein the control circuitry comprises circuitry to ensure that an interval over which the first timing signal is disabled from oscillating extends for an integer number of cycles of the controller-core clock signal, wherein the integer number is greater than or equal to one.