发明名称 |
Semiconductor memory device and method of testing the same |
摘要 |
A semiconductor memory device includes a write controller configured to transmit a first input data that is supplied through a first pad, to a first global I/O line and a second global I/O line when a write operation is executed in a test mode. The semiconductor memory device further includes a first write driver configured to store the first input data via the first global I/O line in a first cell block when the write operation is executed in the test mode. The semiconductor memory device further includes a first I/O line driver configured to supply signals to the first global I/O line and a first test I/O line in response to a first output data supplied from the first cell block when a read operation is executed in the test mode. |
申请公布号 |
US8917572(B2) |
申请公布日期 |
2014.12.23 |
申请号 |
US201213719066 |
申请日期 |
2012.12.18 |
申请人 |
SK hynix Inc. |
发明人 |
Chu Shin Ho |
分类号 |
G11C8/00;G11C7/00;G11C29/08;G11C29/34;G11C29/12;G11C29/26 |
主分类号 |
G11C8/00 |
代理机构 |
Kilpatrick Townsend & Stockton LLP |
代理人 |
Kilpatrick Townsend & Stockton LLP |
主权项 |
1. A semiconductor memory device comprising:
a write controller configured to transmit a first input data from a first pad to a first global I/O line and a second global I/O line when a write operation is executed during a test mode; a first write driver configured to transfer the first input data from the first global I/O line to a first cell block so as to cause the first input data to be stored in the first cell block when the write operation is executed during the test mode; and a first I/O line driver configured to supply signals to the first global I/O line and to a first test I/O line in response to receiving a first output data from the first cell block when a read operation is executed during the test mode. |
地址 |
Icheon-si KR |