Circuit and system for testing a one-time programmable (OTP) memory

摘要

Circuits, systems and techniques for testing a One-Time Programmable (OTP) memory are disclosed. An extra OTP bit can be provided as a test sample to be programmed. The programmed extra OTP bit can be read with any virgin cells in the OTP memory alternatively to generate a stream of logic 0 and logic 1 data so that every row or column path can be tested and the outcome can be observed in a pseudo-checkerboard pattern or other predetermined pattern. By carefully setting control signals, checkerboard-like pattern can be generated without actual programming any OTP cells in the memory array.

主权项

1. A One-Time Programmable (OTP) memory, comprising:
a plurality of OTP cells, at least one of the OTP cells comprising:
a program selector with an enable signal coupled to a wordline (WL);an OTP element with one end coupled to the program selector and another end coupled to a bitline (BL); andthe OTP cells being organized as a two-dimensional array with the WLs of the OTP cells in the same rows coupled to a WL and the BLs of the OTP cells in the same columns coupled to a BL; at least one sense amplifier coupled to at least one BLs to generate a logic state; at least one row or column decoders to select one row or one column from the OTP memory; and at least one control signal coupled to the row or column decoders to turn on or off any adjacent rows or columns, wherein test patterns are be generated with alternative logic 0 and 1 states by setting a combination of the control signals to turn on at least one row or columns through at least one sense amplifiers to read from at least one OTP cells.