Timing controller and a display device including the same

摘要

A timing controller that includes a noise detection circuit and a setting control unit. The noise detection circuit includes a detection unit and a reset signal generating unit. The detection unit outputs a detection signal having a first logic level based on at least one of a plurality of reference data toggling asynchronous with a clock signal. The reset signal generating unit outputs a reset signal having a second logic level based on the detection signal. The setting control unit stores setting data and initializes the setting data in response to the reset signal having the first logic level, and the setting data are used to process red, green and blue (RGB) image data.

主权项

1. A timing controller, comprising:
a noise detection circuit including:
a first detection unit configured to output a detection signal having a first logic level based on at least one of a plurality of reference data toggling asynchronous with a clock signal; anda reset signal generating unit configured to output a reset signal having a second logic level based on the detection signal; a setting control unit configured to store setting data and initialize the setting data in response to the reset signal having the second logic level, the setting data being used to process red, green and blue (RGB) image data; and a second detection unit which outputs a detection signal, this detection signal having the first logic level based on at least one of another plurality of reference data toggling asynchronous with the clock signal, and wherein the reset signal generating unit provides the reset signal having the second logic level based on the detection signals of the first and second detection units, and wherein each of the first and second detection units comprises: a reference data generating unit which includes first through fourth flip-flops respectively outputting first through fourth reference data, each of the first through fourth flip-flops operating in synchronization with the clock signal, and each of the first through fourth flip-flops having an inverted output terminal connected to an input terminal thereof; and a detection signal generating unit configured to provide the detection signal based on a first pair of the reference data and a second pair of the reference data, first pair of the reference data having the same phase with respect to each other, and the second pair of the reference data having an inverse phase with respect to the first pair of the reference data.